The present invention relates generally to high voltage integrated circuits and, more specifically to a bipolar transistor in an intergrated circuit capable of achieving operation to BV.sub.CBO rather than BV.sub.CEO limit.
It is well-known that BV.sub.CEO is less than BV.sub.CBO in transistors with a uniform collector doping due to carrier multiplication by the emitter base junction. The relation between the two breakdowns is: ##EQU1## In silicon devices n.apprxeq.4 for NPN's and n.apprxeq.6 for PNP's. It is found in many devices that BV.sub.CEO &lt;1/2BV.sub.CBO as a result of this relationship. It is also well known that BV.sub.CBO .varies.N.sub.C.sup.-3/4. Consequently, to increase BV.sub.CBO and thus BV.sub.CEO, one must decrease N.sub.C, the doping of the collector region, and thus increase its resistivity in inverse proportion. Transistor collector resistance is directly proportional to collector resistivity and inversely proportional to device area. Thus, when collector resistivity is increased to increase BV.sub.CEO, device area must also be increased to achieve a given value of collector resistance. Large device areas are costly to manufacture and therefore one seeks ways to minimize collector area. One method is to use designs which allow operation to the BV.sub.CBO rather than the BV.sub.CEO limit of the transistor.